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10-Bit Integrated, Multiformat, HDTV Video Decoder, RGB Graphics Digitizer, and 2:1 Multiplexed HDMI/DVI Interface
AD9388A
FEATURES
Mutliformat decoder Three 10-bit analog-to-digital converters (ADCs) ADC sampling rates up to 170 MHz Mux with 12 analog input channels 525i-/625i-component SD support 525p-/625p-component progressive scan support 720p-/1080i-/1080p-component HDTV support Digitizes RGB graphics up to 1600 x 1200 at 60 Hz (UXGA) VBI data slicer (including teletext) Analog-to-HDMI fast switching Dual High-Definition Multimedia Interface (HDMI) Rx 2:1 multiplexed HDMI receiver HDMI 1.3, DVI 1.0 225 MHz HDMI receiver Repeater support High-bandwidth digital content protection (HDCP 1.3) 36-bit deep color support S/PDIF (IEC60958-compatible) digital audio output Multichannel I2S audio output (up to 8 channels) Adaptive equalizer for cable lengths up to 30 meters Internal EDID RAM General Highly flexible output interface STDI function support standard identification 2 any-to-any 3 x 3 color-space conversion matrices Programmable interrupt request output pins
GENERAL DESCRIPTION
The AD9388A is a high quality, single-chip graphics digitizer with an integrated 2:1 multiplexed HDMITM receiver. The AD9388A contains one main component processor (CP) that processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The AD9388A can keep the HDCP link between an HDMI source and the selected HDMI port active in analog mode operation. This allows for fast switching between the analog and HDMI modes. The AD9388A supports the decoding of a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The support for component video includes 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i standards, as well as many other HD and SMPTE standards. Graphic digitization is also supported by the AD9388A. The AD9388A is capable of digitizing RGB graphics signals from VGA to UXGA rates and converting them into a digital RGB or YCrCb pixel output stream. The AD9388A incorporates a dual input, HDMI 1.3-compatible receiver that supports HDTV formats up to 1080p and display resolutions up to UXGA (1600 x 1200 at 60 Hz). The reception of encrypted video is possible with the inclusion of HDCP. In addition, the inclusion of adaptive equalization ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has an advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. Derivative parts of the AD9388A are available; AD9388ABSTZA5 is composed of one analog and one digital input. To facilitate professional applications, where HDCP processing and decryption are not required, the AD9388ABSTZ-5P derivative is available. This allows users who are not HDCP adopters to purchase the AD9388A. See the Ordering Guide for details on these derivative parts. Fabricated in an advanced CMOS process, the AD9388A is available in a space saving, 144-lead, surface-mount, RoHScompliant, plastic LQFP and is specified over the -40C to +85C temperature range.
APPLICATIONS
Advanced TVs PDP HDTVs LCD TVs (HDTV ready) LCD/DLP(R) rear projection HDTVs CRT HDTVs LCoS(R) HDTVs Audio/video receivers (AVRs) LCD/DLP front projectors HDTV STBs with PVR DVD recorders with progressive scan input support
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 (c)2007-2008 Analog Devices, Inc. All rights reserved.
AD9388A TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Electrical Characteristics ............................................................. 4 Analog and HDMI Specifications .............................................. 6 Data and I C Timing Characteristics ......................................... 7 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 Package Thermal Performance ................................................... 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Functional Overview ...................................................................... 16 Analog Front End ....................................................................... 16 HDMI Receiver ........................................................................... 16
2
Component Processor Pixel Data Output Modes.................. 16 Component Video Processing .................................................. 16 RGB Graphics Processing ......................................................... 16 General Features ......................................................................... 16 Theory of Operation ...................................................................... 17 Analog Front End ....................................................................... 17 HDMI Receiver........................................................................... 17 Component Processor (CP) ...................................................... 17 VBI Data Processor .................................................................... 17 Pixel Output Formatting................................................................ 18 Register Map Architecture ........................................................ 21 Typical Connection Diagram ................................................... 22 Recommended External Loop Filter Components ................ 23 AD9388A/ADV7441A Evaluation Platform .............................. 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
7/08--Rev. SpA to Rev. B 5/08--Rev. Sp0 to Rev. SpA Changes to General Description .................................................... 1 Added Figure 6 ................................................................................ 13 Added Table 7.................................................................................. 13 Changes to Component Processor Pixel Data Output Modes Section .............................................................................................. 16 Changes to Component Processor (CP) Section........................ 17 Added AD9388A/ADV7441A Evaluation Platform Section .... 24 Changes to Ordering Guide .......................................................... 25 10/07--Revsion Sp0: Initial Version
Rev. B | Page 2 of 28
ANALOG INTERFACE PIXEL DATA RGB INPUT MATRIX CLAMP CLAMP ADC2 10 10 DIGITAL PROCESSING BLOCK HS/CS, VS LLC GENERATION CONTROL EMBEDDED SYNC MUX SYNC SOURCE AND POLARITY DETECT SYNC PROCESSING AND CLOCK GENERATION DATA PREPROCESSOR COMPONENT PROCESSOR SYNC EXTRACT STANDARD IDENTIFICATION MACROVISION AND CGMS DETECTION PROG. DELAY DIGITAL FINE CLAMP GAIN CONTROL OFFSET ADDER AV CODE INSERTION INT1 SOG SOY HS_IN/CS_IN VS_IN ADC1 10 CLAMP ADC0 10 10 P0 TO P9 10 P10 TO P19 P20 TO P29
AD9388A
FUNCTIONAL BLOCK DIAGRAM
YPrPb
CONTROL AND DATA CONTROL INTERFACE I2C CONTROL COLOR SPACE CONVERTER (A) (A) (B) (B) (C) (C)
HS/CS VS/FIELD DE/FIELD
SCL SDA ALSB
Figure 1.
FILTER DECIMATION AND DOWNSAMPLING FILTERS MUX DATA RECOVERY ALIGNMENT HDMI DECODE DE XOR VS HS 4:2:2 TO 4:4:4 CONVERSION
DDCA_SCL
DDCA_SDA
DDCB_SDA
DDCB_SCL
MCL
06915-001
Rev. B | Page 3 of 28
EDID/ REPEATER CONTROLLER HDCP ENGINE HDCP EEPROM PACKET PROCESSOR MDA PACKET/ INFOFRAME MEMORY AUDIO PROCESSING
RXA_0 RXA_1 RXA_2
EQUALIZER
SAMPLER
NOISE AND CALIBRATION
OUTPUT FORMATTER
ACTIVE PEAK AND HSYNC DEPTH
LLC SYNC_OUT/ INT2 VBI DATA PROCESSOR VBI DECODER ANCILLARY DATA FORMATTER
RXA_C RXB_C
MUX
PLL
RXB_0 RXB_1 RXB_2
EQUALIZER
SAMPLER
ANCILLARY DATA
I2S LRCLK SCLK MCLKOUT SPDIF
AD9388A
AD9388A SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 1.
Parameter 1 STATIC PERFORMANCE 2 Resolution (Each ADC) Integral Nonlinearity Symbol N INL Test Conditions Min Typ Max 10 -4/+6 Unit Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB V V V V A A pF V V A pF V V V V V V mA mA mA mA mA mA mA mA mA
Differential Nonlinearity
DNL
BSL at 27 MHz (@ a 10-bit level) BSL at 54 MHz (@ a 10-bit level) BSL at 74 MHz (@ a 10-bit level) BSL at 110 MHz (@ a 10-bit level) BSL at 170 MHz (@ an 8-bit level) At 27 MHz (@ a 10-bit level) At 54 MHz (@ a 10-bit level) At 74 MHz (@ a 10-bit level) At 110 MHz (@ a 10-bit level) At 170 MHz (@ an 8-bit level) 2 0.7
-0.5/+2 -0.5/+2 -0.5/+1.5 -0.7/+2 -0.25/+0.5 -0.5/+0.5 0.5 0.5 0.5 -0.25/+0.2
-0.95/+2
DIGITAL INPUTS Input High Voltage 3 Input Low Voltage3 Input Current Input Capacitance 4 DIGITAL OUTPUTS Output High Voltage 5 Output Low Voltage5 High Impedance Leakage Current Output Capacitance4 POWER REQUIREMENTS4 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Terminator Power Supply Comparator Power Supply Digital Core Supply Current
VIH HS_IN, VS_IN low trigger mode VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD TVDD CVDD IDVDD ISOURCE = 0.4 mA ISINK = 3.2 mA HS_IN, VS_IN low trigger mode Pin 21 (RESET) All input pins other than Pin 21
-60 -10
0.8 0.3 +60 +10 10
2.4 0.4 10 20 1.62 2.97 1.71 1.71 3.135 1.71 1.8 3.3 1.8 1.8 3.3 1.8 141 203 242 242 17 42 17 20 56 1.98 3.63 1.89 1.89 3.465 1.89 252 263 329 326 37 62 34 34 78
Digital I/O Supply Current
IDVDDIO
HDMI Comparators
ICVDD
Graphics RGB sampling @ 108 MHz 6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz 7, 8 HDMI RGB sampling @ 225 MHz7, 8 Graphics RGB sampling @ 108 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 Graphics RGB sampling @ 108 MHz6
Rev. B | Page 4 of 28
AD9388A
Parameter 1 TMDS PLL and Equalizer Supply Current Symbol Test Conditions YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 Graphics RGB sampling @ 108 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 Graphics RGB sampling @ 108 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8, 9 HDMI RGB sampling @ 225 MHz7, 8, 9 Graphics RGB sampling @ 108 MHz6 YPrPb 1080p sampling @ 148.5 MHz6 HDMI RGB sampling @ 165 MHz7, 8 HDMI RGB sampling @ 225 MHz7, 8 Min Typ 56 86 95 174 180 0 0 12 12 42 63 14 19 10 15 11.6 25 Max 79 105 118 278 284 2 2 18 18 47 69 21 24 19 20 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA ms
Analog Supply Current
IAVDD
Terminator Supply Current
ITVDD
Audio and Video Supply Current
IPVDD
Power-Down Current Power-Up Time
1 2 3
IPWRDN tPWRUP
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). All ADC linearity tests performed at input range of full scale - 12.5% and at zero scale + 12.5%. Pin 1, Pin 105, Pin 106, and Pin 144 are 5 V tolerant. 4 Guaranteed by characterization. 5 VOH and VOL levels obtained using default drive strength value (0x15) in User Map Register 0xF4. 6 Current measurements for analog inputs were made with HDMI/analog simultaneous mode disabled (User Map Register 0xBA Bit 7 programmed with Value 0) and no HDMI sources connected to the part. 7 Current measurements for HDMI inputs were made with a source connected to the active HDMI port and no source connected to the inactive HDMI port. 8 Audio stream is uncompressed stereo audio sampling frequency of fS = 48 kHz and MCLKOUT = 256 fS. 9 The terminator supply current may vary with the HDMI source in use.
Rev. B | Page 5 of 28
AD9388A
ANALOG AND HDMI SPECIFICATIONS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V. Operating temperature range is -40C to +85C, unless otherwise noted. Table 2.
Parameter 1, 2 ANALOG Clamp Circuitry External Clamp Capacitor Input Impedance (Except Pin 74) Input Impedance of Pin 74 CML ADC Full-Scale Level ADC Zero-Scale Level ADC Dynamic Range Clamp Level (When Locked) Test Conditions Min Typ Max Unit
Clamps switched off
Component input (Y signal) Component input (Pr signal) Component input (Pb signal) PC RGB input (R, G, B signals)
0.1 10 20 0.88 CML + 0.5 CML - 0.5 1 CML - 0.120 CML CML CML - 0.120 0.4 0.2 tpixel 5 + 1.78 ns
F M k V V V V V V V V tbit 4
HDMI SPECIFICATIONS 3 Intrapair (Positive-to-Negative) Differential Input Skew Channel-to-Channel Differential Input Skew
1
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range. Guaranteed by characterization. 3 Guaranteed by design. 4 tbit is 1/10 the pixel period of the TMDS clock. 5 tpixel is the period of the TMDS clock.
2
Rev. B | Page 6 of 28
AD9388A
DATA AND I2C TIMING CHARACTERISTICS
AVDD = 1.71 V to 1.89 V, DVDD = 1.62 V to 1.98 V, DVDDIO = 2.97 V to 3.63 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to 1.89 V; operating temperature range is -40C to +85C, unless otherwise noted. Table 3.
Parameter 1, 2 SYSTEM CLOCK AND CRYSTAL Crystal Nominal Frequency Crystal Frequency Stability Horizontal Sync Input Frequency LLC Frequency Range I2C PORTS (FAST MODE) 3 xCL Frequency 4 xCL Minimum Pulse Width High4 xCL Minimum Pulse Width Low4 Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time4 xCL and xDA Rise Times4 xCL and xDA Fall Times4 Setup Time (Stop Condition) I2C PORTS (NORMAL MODE) xCL Frequency xCL Minimum Pulse Width High xCL Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) xDA Setup Time xCL and xDA Rise Times xCL and xDA Fall Times Setup Time (Stop Condition) RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transition Time SDR (CP) 5 I2S PORT (MASTER MODE) SCLK Mark Space Ratio LRCLK Data Transition Time LRCLK Data Transition Time I2Sx Data Transition Time 6 I2Sx Data Transition Time6 MCLKOUT Frequency
1 2 3
Symbol
Test Conditions
Min
Typ 28.6363
Max
Unit MHz ppm kHz MHz kHz s s s s ns ns ns s kHz s s s s ns ns ns s ms
14.8 12.825
50 110 170 400
t1 t2 t3 t4 t5 t6 t7 t8
0.6 1.3 0.6 0.6 100 300 300 0.6 100
t1 t2 t3 t4 t5 t6 t7 t8
4 4.7 4 4.7 250 1000 300 4 5
t9:t10
45:55
55:45
% duty cycle ns ns % duty cycle ns ns ns ns MHz
t11 t12 t13:t14 t15 t16 t17 t18
End of valid data to negative clock edge Negative clock edge to start of valid data 45:55 End of valid data to negative SCLK edge Negative SCLK edge to start of valid data End of valid data to negative SCLK edge Negative SCLK edge to start of valid data 4.096
2 0.5 55:45 10 10 5 5 24.576
The minimum/maximum specifications are guaranteed over the -40C to +85C temperature range (TMIN to TMAX). Guaranteed by characterization. Refers to all I2C pins (DDC and control port). 4 The prefix x refers to pin names beginning with S, DDCA_S, and DDCB_S. 5 CP timing figures were obtained using the maximum drive strength value (0x3F) in User Map Register 0xF4. 6 The suffix x refers to pin names ending with 0, 1, 2, and 3.
Rev. B | Page 7 of 28
AD9388A
Timing Diagrams
t3
xDA
t5
t3
t6
xCL
t1
t2
t7
t4
t8
06915-002
NOTES 1. THE PREFIX x REFERS TO PIN NAMES BEGINNING WITH S, DDCA_S, AND DDCB_S.
Figure 2. I2C Timing
t9
t10
LLC
t11 t12
06915-004
P0 TO P29, VS, HS, FIELD/DE
Figure 3. Pixel Port and Control CP Output Timing (CP Core)
t13
SCLK
t14 t15
LRCLK
t16
I2Sx LEFT-JUSTIFIED MODE
t17
MSB MSB - 1
t18
I2Sx I2S MODE I2Sx RIGHT-JUSTIFIED MODE MSB
t17
MSB - 1
t18
MSB
t17
LSB
NOTES 1. THE SUFFIX x REFERS TO PIN NAMES ENDING WITH 0, 1, 2, AND 3.
t18
Figure 4. I2S Timing
Rev. B | Page 8 of 28
06915-005
AD9388A ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter AVDD to AGND DVDD to DGND PVDD to PGND DVDDIO to DGND CVDD to CGND TVDD to TGND DVDDIO to AVDD DVDDIO to TVDD DVDDIO to DVDD CVDD to DVDD PVDD to DVDD AVDD to CVDD AVDD to PVDD AVDD to DVDD AVDD to TVDD TVDD to DVDD Digital Inputs Voltage to DGND Digital Outputs Voltage to DGND Analog Inputs Voltage to AGND Maximum Junction Temperature (TJ_MAX) Storage Temperature Range Infrared Reflow, Soldering (20 sec) Rating 2.2 V 2.2 V 2.2 V 4V 2.2 V 4V -0.3 V to +3.6 V -3.6 V to +3.6 V -2 V to +2 V -2 V to +0.3 V -2 V to +0.3 V -2 V to +2 V -2 V to +2 V -2 V to +2 V -3.6 V to +0.3 V -2 V to +2 V DGND - 0.3 V to DVDDIO + 0.3 V DGND - 0.3 V to DVDDIO + 0.3 V AGND - 0.3 V to AVDD + 0.3 V 125C -65C to +150C 260C
THERMAL RESISTANCE
Table 5.
Package Type 144-Lead LQFP (ST-144)
1
JT1 1.62
Unit C/W
Junction-to-package surface thermal resistance.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption during AD9388A operation, turn off unused ADCs. On a four-layer PCB that includes a solid ground plane, the JA value is 25.3C/W. However, due to variations within the PCB metal and, therefore, variations in PCB heat conductivity, the value of JA may differ for various PCBs. The most efficient measurement technique is to use the surface temperature of the package to estimate the die temperature because this is not affected by the variance associated with the JA value. The maximum junction temperature (TJ_MAX) of 125C must not be exceeded. The following equation calculates the junction temperature using the measured surface temperature of the package and applies only when no heat sink is used on DUT: TJ_MAX = TS + (JT x WTOTAL) where: TS is the surface temperature of the package expressed in degrees Celsius. JT is the junction-to-package surface thermal resistance. WTOTAL = {(AVDD x IAVDD) + (DVDD x IDVDD) + (DVDDIO x IDVDDIO) + (PVDD x IPVDD) + (CVDD x ICVDD) + (TVDD x ITVDD)}. Contact an Analog Devices, Inc., representative for more details on package thermal performance at video.products@analog.com.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. B | Page 9 of 28
AD9388A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DDCB_SCL DGND DVDD CVDD CGND TVDD RXB_2P RXB_2N TGND RXB_1P RXB_1N TGND RXB_0P RXB_0N TGND RXB_CP RXB_CN TVDD CGND CVDD RTERM TVDD RXA_2P RXA_2N TGND RXA_1P RXA_1N TGND RXA_0P RXA_0N TGND RXA_CP RXA_CN TVDD CGND CVDD
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110
DDCB_SDA SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP SDA SCL ALSB DGND DVDDIO DE/FIELD HS/CS VS/FIELD INT1 SYNC_OUT/INT2 RESET DGND DVDD P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 DGND DVDDIO P10
109
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 PIN 1 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93
TOP VIEW (Not to Scale)
AD9388A
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TEST5 TEST4 DDCA_SDA DDCA_SCL CVDD CGND AUDIO_ELPF PVDD PGND AIN6 AIN12 SOY AIN5 AIN11 AIN4 AIN10 REFP TEST3 REFN TEST2 AVDD AGND CML REFOUT AVDD AGND AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 SOG TEST1 TEST0
P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 EXT_CLK DGND DVDDIO LLC P22 P23 P24 P25 DGND DVDD P26 P27 P28 P29 VS_IN HS_IN/CS_IN DGND XTAL1 XTAL DVDDIO PVDD PGND ELPF PVDD PGND
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 14, 22, 34, 49, 56, 64, 143 82, 83, 87 69, 72, 100 103, 110, 126, 140 114, 117, 120, 130, 133, 136 15, 35, 50, 67 23, 57, 142 84, 88 68, 71, 101 104, 109, 125, 141 111, 123, 127, 139 73, 74, 91, 108 89 107 76 to 81, 93 to 96, 98, 99 Mnemonic DGND AGND PGND CGND TGND DVDDIO DVDD AVDD PVDD CVDD TVDD TEST0, TEST1, TEST3, TEST5 TEST2 TEST4 AIN1 to AIN12 Type 1 G G G G G P P P P P P I O I/O I Description Digital Ground. Analog Ground. PLL Ground. Comparator Ground. Terminator Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Audio and Video PLL Supply Voltage (1.8 V). HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V). Terminator Supply Voltage (3.3 V). Test Pins. Do not connect. Test Pin. Do not connect. Test Pin. Do not connect. Analog Video Input Channel.
Rev. B | Page 10 of 28
06915-006
AD9388A
Pin No. 24 to 33, 36 to 47, 52 to 55, 58 to 61 19 20 17 Mnemonic P0 to P29 INT1 SYNC_OUT/INT2 HS/CS Type 1 O O O O Description Video Pixel Output Port. Interrupt. Can be active low or active high. The set of events that triggers an interrupt is under user control. Sliced Synchronization Output Signal (SYNC_OUT). Interrupt Signal (INT2). Horizontal Synchronization Output Signal (HS). Composite Synchronization (CS). A single signal containing both horizontal and vertical synchronization pulses. Vertical Synchronization Output Signal (VS). Field Synchronization (FIELD). Field synchronization output signal in all interlaced video modes. Data Enable Signal (DE). Indicates active pixel data. Field Synchronization (FIELD). Field synchronization output signal in all interlaced video modes. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for the control port. This pin sets the second LSB of each AD9388A register map. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the AD9388A circuitry. Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the AD9388A. In crystal mode, the crystal must be a fundamental crystal. Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the AD9388A. The recommended external loop filter must be connected to this ELPF pin. The recommended external loop filter must be connected to this AUDIO_ELPF pin. Internal Voltage Reference Output. Common-Mode Level for the Internal ADCs. Internal Voltage Output. Internal Voltage Output. HS Input Signal. Used in analog mode for 5-wire timing mode. CS Input Signal. Used in analog mode for 4-wire timing mode. For optimal performance, a 100 series resistor is recommended on the HS_IN/CS_IN pin. VS Input Signal. This pin is used in analog mode for 5-wire timing mode. For optimal performance, a 100 series resistor is recommended on the VS_IN pin. Synchronization-on-Green Input. This pin is used in embedded synchronization mode. Synchronization-on-Luma Input. This pin is used in embedded synchronization mode. Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface.
18
VS/FIELD
O
16
DE/FIELD
O
11 12 13 21 51 65
SDA SCL ALSB RESET LLC XTAL1
I/O I I I O O
66
XTAL
I
70 102 85 86 90 92 63
ELPF AUDIO_ELPF REFOUT CML REFN REFP HS_IN/CS_IN
O O O O I I I
62
VS_IN
I
75 97 112 113 115 116 118 119
SOG SOY RXA_CN RXA_CP RXA_0N RXA_0P RXA_1N RXA_1P
I I I I I I I I
Rev. B | Page 11 of 28
AD9388A
Pin No. 121 122 128 129 131 132 134 135 137 138 106 1 105 144 2 3 4 5 6 7 8 9 10 48 124
1
Mnemonic RXA_2N RXA_2P RXB_CN RXB_CP RXB_0N RXB_0P RXB_1N RXB_1P RXB_2N RXB_2P DDCA_SDA DDCB_SDA DDCA_SCL DDCB_SCL SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP EXT_CLK RTERM
Type 1 I I I I I I I I I I I/O I/O I I O O O O O O O O I I I
Description Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. Digital Input Clock Complement of Port B in the HDMI Interface. Digital Input Clock True of Port B in the HDMI Interface. Digital Input Channel 0 Complement of Port B in the HDMI Interface. Digital Input Channel 0 True of Port B in the HDMI Interface. Digital Input Channel 1 Complement of Port B in the HDMI Interface. Digital Input Channel 1 True of Port B in the HDMI Interface. Digital Input Channel 2 Complement of Port B in the HDMI Interface. Digital Input Channel 2 True of Port B in the HDMI Interface. HDCP Slave Serial Data Port A. HDCP Slave Serial Data Port B. HDCP Slave Serial Clock Port A. HDCP Slave Serial Clock Port B. SPDIF Digital Audio Output. I2S Audio (Channel 1 and Channel 2). I2S Audio (Channel 3 and Channel 4). I2S Audio (Channel 5 and Channel 6). I2S Audio (Channel 7, and Channel 8). LRCLK, Data Output Clock for Left and Right Audio Channels. Audio Serial Clock Output. Audio Master Clock Output. External Clamp Signal. This is an optional mode of operation for the AD9388A. Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the AD9388A. Sets Internal Termination Resistance. Connect this pin to TGND using a 500 resistor.
G = ground, P = power, I = input, and O = output.
Rev. B | Page 12 of 28
AD9388A
TEST7 DGND DVDD CVDD CGND TVDD TEST8 TEST9 TGND TEST10 TEST11 TGND TEST12 TEST13 TGND TEST14 TEST15 TVDD CGND CVDD RTERM TVDD RXA_2P RXA_2N TGND RXA_1P RXA_1N TGND RXA_0P RXA_0N TGND RXA_CP RXA_CN TVDD CGND CVDD
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110
TEST6 SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP SDA SCL ALSB DGND DVDDIO DE/FIELD HS/CS VS/FIELD INT1 SYNC_OUT/INT2 RESET DGND DVDD P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 DGND DVDDIO P10
109
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108 PIN 1 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93
AD9388ABSTZ-A5
TOP VIEW (Not to Scale)
92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
TEST5 TEST4 DDCA_SDA DDCA_SCL CVDD CGND AUDIO_ELPF PVDD PGND TEST16 TEST17 SOY TEST18 TEST19 TEST20 TEST21 REFP TEST3 REFN TEST2 AVDD AGND CML REFOUT AVDD AGND AGND AIN3 TEST22 AIN2 TEST23 AIN1 TEST24 SOG TEST1 TEST0
P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 EXT_CLK DGND DVDDIO LLC P22 P23 P24 P25 DGND DVDD P26 P27 P28 P29 VS_IN HS_IN/CS_IN DGND XTAL1 XTAL DVDDIO PVDD PGND ELPF PVDD PGND
Figure 6. AD9388ABSTZ-A5 Derivative Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 14, 22, 34, 49, 56, 64, 143 82, 83, 87 69, 72, 100 103, 110, 126, 140 114, 117, 120, 130, 133, 136 15, 35, 50, 67 23, 57, 142 84, 88 68, 71, 101 104, 109, 125, 141 111, 123, 127, 139 128, 129, 131, 132, 134, 135, 137, 138, 108, 91, 74, 73 76, 78, 80, 93, 94, 95, 96, 98, 99 89 107 77, 79, 81 Mnemonic DGND AGND PGND CGND TGND DVDDIO DVDD AVDD PVDD CVDD TVDD TEST15 to TEST8, TEST5, TEST3, TEST1, TEST0 Test 24 to Test16 TEST2 TEST4 AIN1 to AIN3 Type 1 G G G G G P P P P P P I Description Digital Ground. Analog Ground. PLL Ground. Comparator Ground. Terminator Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (1.8 V). Audio and Video PLL Supply Voltage (1.8 V). HDMI Comparator, TMDS PLL, and Equalizer Supply Voltage (1.8 V). Terminator Supply Voltage (3.3 V). Test Pins. Do not connect.
I O I/O I
Test Pins. Connect to AGND through a 10 k resistor. Test Pin. Do not connect. Test Pin. Do not connect. Analog Video Input Channel.
Rev. B | Page 13 of 28
06915-100
AD9388A
Pin No. 24 to 33, 36 to 47, 52 to 55, 58 to 61 19 20 17 Mnemonic P0 to P29 INT1 SYNC_OUT/INT2 HS/CS Type 1 O O O O Description Video Pixel Output Port. Interrupt. Can be active low or active high. The set of events that triggers an interrupt is under user control. Sliced Synchronization Output Signal (SYNC_OUT). Interrupt Signal (INT2). Horizontal Synchronization Output Signal (HS). Composite Synchronization (CS). A single signal containing both horizontal and vertical synchronization pulses. Vertical Synchronization Output Signal (VS). Field Synchronization (FIELD). Field synchronization output signal in all interlaced video modes. Data Enable Signal (DE). Indicates active pixel data. Field Synchronization (FIELD). Field synchronization output signal in all interlaced video modes. I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port. I2C Port Serial Clock Input. (Maximum clock rate of 400 kHz.) SCL is the clock line for the control port. This pin sets the second LSB of each AD9388A register map. System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset the AD9388A circuitry. Line-Locked Output Clock for Pixel Data. Range is 13.5 MHz to 170 MHz. This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the AD9388A. In crystal mode, the crystal must be a fundamental crystal. Input Pin for the 28.63636 MHz Crystal. This pin can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the AD9388A. The recommended external loop filter must be connected to this ELPF pin. The recommended external loop filter must be connected to AUDIO_ELPF. Internal Voltage Reference Output. Common-Mode Level for the Internal ADCs. Internal Voltage Output. Internal Voltage Output. HS Input Signal. Used in analog mode for 5-wire timing mode. CS Input Signal. Used in analog mode for 4-wire timing mode. For optimal performance, a 100 series resistor is recommended on the HS_IN/CS_IN pin. VS Input Signal. This pin is used in analog mode for 5-wire timing mode. For optimal performance, a 100 series resistor is recommended on the VS_IN pin. Synchronization-on-Green Input. This pin is used in embedded synchronization mode. Synchronization-on-Luma Input. This pin is used in embedded synchronization mode. Digital Input Clock Complement of Port A in the HDMI Interface. Digital Input Clock True of Port A in the HDMI Interface. Digital Input Channel 0 Complement of Port A in the HDMI Interface. Digital Input Channel 0 True of Port A in the HDMI Interface. Digital Input Channel 1 Complement of Port A in the HDMI Interface. Digital Input Channel 1 True of Port A in the HDMI Interface. Digital Input Channel 2 Complement of Port A in the HDMI Interface. Digital Input Channel 2 True of Port A in the HDMI Interface. HDCP Slave Serial Data Port A. Test Pin. Do not connect. HDCP Slave Serial Clock Port A. Test Pin. Connect this pin to DGND using a 10 k resistor.
Rev. B | Page 14 of 28
18
VS/FIELD
O
16
DE/FIELD
O
11 12 13 21 51 65
SDA SCL ALSB RESET LLC XTAL1
I/O I I I O O
66 70 102 85 86 90 92 63
XTAL ELPF AUDIO_ELPF REFOUT CML REFN REFP HS_IN/CS_IN
I O O O O I I I
62 75 97 112 113 115 116 118 119 121 122 106 1 105 144
VS_IN SOG SOY RXA_CN RXA_CP RXA_0N RXA_0P RXA_1N RXA_1P RXA_2N RXA_2P DDCA_SDA TEST6 DDCA_SCL TEST7
I I I I I I I I I I I I/O I/O I I
AD9388A
Pin No. 2 3 4 5 6 7 8 9 10 48 124
1
Mnemonic SPDIF I2S0 I2S1 I2S2 I2S3 LRCLK SCLK MCLKOUT EXT_CLAMP EXT_CLK RTERM
Type 1 O O O O O O O O I I I
Description SPDIF Digital Audio Output. I2S Audio (Channel 1 and Channel 2). I2S Audio (Channel 3 and Channel 4). I2S Audio (Channel 5 and Channel 6). I2S Audio (Channel 7 and Channel 8). LRCLK, Data Output Clock for Left and Right Audio Channels. Audio Serial Clock Output. Audio Master Clock Output. External Clamp Signal. This is an optional mode of operation for the AD9388A. Clock Input for External Clock and Clamp Mode. This is an optional mode of operation for the AD9388A. Sets Internal Termination Resistance. Connect this pin to TGND using a 500 resistor.
G = ground, P = power, I = input, and O = output.
Rev. B | Page 15 of 28
AD9388A FUNCTIONAL OVERVIEW
The following overview provides a brief description of the functionality of the AD9388A. More details are available in the Theory of Operation section. In addition, the AD9388A features brightness, saturation, and hue controls. System level component format detection is enabled by standard identification (STDI), and a synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization signals that accompany the input video. Certified Macrovision(R) copy-protection detection is available on component formats (525i, 625i, 525p, and 625p). When no video input is present, stable timing is provided by the free run output mode.
ANALOG FRONT END
The analog front end of the AD9388A provides three high quality 10-bit ADCs to enable true 10-bit video decoding, a multiplexer with 12 analog input channels to enable a multisource connection without the requirement of an external multiplexer, and three current and voltage clamp control loops to ensure that dc offsets are removed from the video signal.
HDMI RECEIVER
The AD9388A is compatible with the HDMI 1.3 specification. The AD9388A supports all HDTV formats up to 1080p in nondeep color mode and 1080p in 36-bit deep color mode. Furthermore, it supports all display resolutions up to UXGA (1600 x 1200 at 60 Hz). This device includes the following features: * * * * Adaptive front-end equalization for HDMI operation over cable lengths of up to 30 meters. Synchronization conditioning for higher performance in strenuous conditions. Audio mute for removing extraneous noises. Programmable data island packet interrupt generator.
RGB GRAPHICS PROCESSING
The AD9388A provides 170 MSPS conversion rate support of RGB input resolutions up to 1600 x 1200 at 60 Hz (UXGA). The AD9388A offers automatic or manual clamp and gain controls for graphics modes. Similar to the component video processing features, the RBG graphics processing for the AD9388A features contrast and brightness controls, automatic detection of synchronization source and polarity by the SSPD block, standard identification enabled by the STDI block, and user-defined pixel sampling support for nonstandard video sources. Additional RGB graphics processing features of the AD9388A include the following: * * * * Sampling PLL clock with 500 ps p-p jitter at 150 MSPS. 32-phase DLL support of optimum pixel clock sampling. Color-space conversion of RGB to YCrCb and decimation to a 4:2:2 format for videocentric, back-end IC interfacing. Data enable (DE) output signal supplied for direct connection to HDMI/DVI transmitter IC.
COMPONENT PROCESSOR PIXEL DATA OUTPUT MODES
The AD9388A features single data rate outputs as follows: * 8-/10-bit 4:2:2 YCrCb for 525i, 625i. * 16-/20-bit 4:2:2 YCrCb for all standards. * 24-/30-bit 4:4:4 YCrCb/RGB for all standards.
COMPONENT VIDEO PROCESSING
The AD9388A supports 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats; automatic adjustment of gain (contrast) and offset (brightness); manual adjustment controls; analog component YPrPb/RGB video formats with embedded synchronization or with separate HS, VS, or CS; YCrCb-to-RGB and RGB-to-YCrCb conversions by any-to-any, 3 x 3, color-space conversion matrices; and user-defined pixel sampling for nonstandard video sources.
GENERAL FEATURES
The AD9388A offers a high quality multiformat video decoder and digitizer that features HS, VS, and FIELD output signals with programmable position, polarity, and width; programmable interrupt request output pins (INT1 and INT2); low power consumption: 1.8 V digital core and analog input, 3.3 V digital input/output, low power power-down mode; and a temperature range of -40C to +85C in a 144-lead, 20 mm x 20 mm, RoHS-compliant LQFP.
Rev. B | Page 16 of 28
AD9388A THEORY OF OPERATION
ANALOG FRONT END
The AD9388A analog front end comprises three 10-bit ADCs that digitize the analog video signal before applying it to the CP. The analog front end uses differential channels to each ADC to ensure high performance in a mixed-signal application. The front end also includes a 12-channel input multiplexer that enables multiple video signals to be applied to the AD9388A. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in the CP. For component 525i, 625i, 525p, and 625p sources, 2x oversampling is performed, but 4x oversampling is available for component 525i and 625i. All other video standards are 1x oversampled. Oversampling the video signals reduces the cost and complexity of external antialiasing (AA) filters with the benefit of an increased signal-to-noise ratio (SNR).
COMPONENT PROCESSOR (CP)
The CP is capable of decoding and digitizing a wide range of component video formats in any color space. Component video standards supported by the CP include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UXGA at 60 Hz, and many other standards. The CP section of the AD9388A contains an AGC block. This block is followed by a digital clamp circuit that ensures that the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness); however, manual adjustment controls are also supported. If no embedded synchronization is present, the video gain can be set manually. A fully programmable, any-to-any 3 x 3 color-space converter is placed before the CP section. This enables YPrPb-to-RGB and RGB-to-YCrCb conversions. Many other standards of color space can be implemented using the color-space converter. A second fully programmable, any-to-any 3 x 3 color space converter is placed in the back end of the CP core. This color space converter features advanced color controls such as contrast, saturation, brightness, and hue controls. The output section of the CP can be configured in single data rate (SDR) mode with one data packet per clock cycle. In SDR mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In these modes, HS/CS, VS/FIELD, and DE/FIELD (where applicable) timing reference signals are provided. The CP section contains circuitry to enable the detection of Macrovision-encoded YPrPb signals for 525i, 625i, 525p, and 625p. It is designed to be fully robust when decoding these types of signals.
HDMI RECEIVER
The HDMI receiver on the AD9388A incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses inherent in HDMI and DVI cables, especially those with long lengths and high frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at the highest HDMI data rates. With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the AD9388A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.3 protocol. The HDMI receiver also offers advanced audio functionality. The receiver contains an audio mute controller that can detect a variety of selectable conditions that may result in audible extraneous noise in the audio output. Upon detection of these conditions, the audio data can be ramped to prevent audio clicks and pops.
VBI DATA PROCESSOR
VBI extraction of CGMS data is performed by the VBI data processor (VDP) section of the AD9388A for interlaced, progressive, and high definition scanning rates. The data extracted is read back over the I2C interface. For more detailed product information about the AD9388A, send an e-mail to video.products@analog.com or contact a local Analog Devices sales representative.
Rev. B | Page 17 of 28
AD9388A PIXEL OUTPUT FORMATTING
Note that unused pins of the pixel output port are driven with a low voltage. Table 8. Component Processor Pixel Output Pin Map (P19 toP0)
Processor 1 CP Mode/Format Mode 1 Video output 8-bit 4:2:2 2 Mode 2 Video output 10-bit 4:2:22 Mode 3 Video output 12-bit 4:2:22 Mode 4 Video output 12-bit 4:2:22 Mode 5 Video output 12-bit 4:2:22 Mode 6 Video output 16-bit 4:2:2 3, 4 Mode 7 Video output 20-bit 4:2:23, 4 Mode 8 Video output 20-bit 4:2:23, 4 Mode 9 Video output 24-bit 4:2:23, 4 Mode 10 Video output 24-bit 4:2:23, 4 Mode 11 Video output 24-bit 4:2:23, 4 Mode 12 Video output 24-bit 4:4:43, 4 Mode 13 Video output 24-bit 4:4:43, 4 Mode 14 Video output 24-bit 4:4:43, 4 Mode 15 Video output 24-bit 4:4:43, 4 Mode 16 Video output 30-bit 4:4:43, 4 19 18 17 16 15 14 Output of Data Port Pins P[19:0] 13 12 11 10 9 8 7 - - - - - 6 - 5 - 4 - 3 - 2 - 10 --
YCrCb[7:0]
CP
YCrCb[9:0]
-
-
-
-
-
-
-
-
--
CP
YCrCb[11:2]
-
-
-
-
-
-
-
-
--
CP
YCrCb[11:4]
-
-
-
-
-
-
-
-
-
-
--
CP
YCrCb[11:4]
-
-
YCrCb[3:0]
-
-
-
-
--
CP
CHA[7:0] (default data is Y[7:0])
-
-
CHB/CHC[7:0] (default data is Cr/Cb[7:0]) - -
CP
CHA[9:0] (default data is Y[9:0])
CHB/CHC[9:0] (default data is Cr/Cb[9:0])
CP
CHA[9:2] (default data is Y[9:2])
-
-
CHB/CHC[9:2] (default data is Cr/Cb[9:2]) - -
CP
Y[11:2]
CrCb[11:2]
CP
Y[11:4]
-
-
CrCb[11:4]
--
CP
Y[11:4]
-
-
Y[3:0]
CrCb[3:0]
--
CP
CHA[7:0] (default data is G[7:0] or Y[7:0])
-
-
CHB[7:0] (default data is R[7:0] or Cr[7:0]) - -
CP
CHA[7:0] (default data is G[7:0] or Y[7:0])
-
-
CHC[7:0] (default data is B[7:0] or Cb[7:0]) - -
CP
CHC[7:0] (default data is B[7:0] or Cb[7:0])
-
-
CHA[7:0] (default data is G[7:0] or Y[7:0])
--
CP
CHC[7:0] (default data is B[7:0] or Cb[7:0])
-
-
CHB[7:0] (default data is R[7:0] or Cr[7:0]) - -
CP
CHA[9:0] (default data is G[9:0] or Y[9:0])
CHB[9:0] (default data is R[9:0] or Cr[9:0])
Rev. B | Page 18 of 28
AD9388A
Processor 1 CP Mode/Format Mode 17 Video output 30-bit 4:4:4 Mode 18 Video output 30-bit 4:4:4 Mode 19 Video output 30-bit 4:2:2 19 18 17 16 15 14 Output of Data Port Pins P[19:0] 13 12 11 10 9 8 7 6 5 4 3 2 10
CHA[9:0] (default data is G[9:0] or Y[9:0])
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CP
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHA[9:0] (default data is G[9:0] or Y[9:0])
CP
CHC[9:0] (default data is B[9:0] or Cb[9:0])
CHB[9:0] (default data is R[9:0] or Cr[9:0])
1 2
CP processor uses digitizer or HDMI as input. Maximum pixel clock rate of 54 MHz. 3 Maximum pixel clock rate of 170 MHz for the analog digitizer. 4 Maximum pixel clock rate of 165 MHz for HDMI.
Table 9. Component Processor Pixel Output Pin Map (P29 to P20)
Processor1 Mode/Format CP Mode 1 Video output 8-bit 4:2:2 2 CP Mode 2 Video output 10-bit 4:2:22 CP Mode 3 Video output 12-bit 4:2:22 CP Mode 4 Video output 12-bit 4:2:2 2 CP Mode 5 Video output 12-bit 4:2:2 2 CP Mode 6 Video output 16-bit 4:2:2 3, 4 CP Mode 7 Video output 20-bit 4:2:23, 4 CP Mode 8 Video output 20-bit 4:2:23, 4 CP Mode 9 Video output 24-bit 4:2:2 3, 4 CP Mode 10 Video output 24-bit 4:2:23, 4 CP Mode 11 Video output 24-bit 4:2:23, 4 CP Mode 12 Video output 24-bit 4:4:43, 4 CP Mode 13 Video output 24-bit 4:4:43, 4 29 - 28 - 27 - 26 - Output of Data Port Pins P[29:20] 25 24 23 - - - 22 - 21 - 20 -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
YCrCb[1:0]
-
-
-
-
-
-
YCrCb[3:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Y[1:0]
CrCb[1:0]
-
-
-
-
-
-
-
-
CrCb[1:0]
-
-
Y[1:0]
-
-
CrCb[3:0]
Y[3:0]
-
-
CrCb[11:4]
-
-
CHC[7:0] (for example, B[7:0] or Cb[7:0])
-
-
CHB[7:0] (for example, R[7:0] or Cr[7:0])
-
-
Rev. B | Page 19 of 28
AD9388A
Processor1 Mode/Format CP Mode 14 Video output 24-bit 4:4:43, 4 CP Mode 15 Video output 24-bit 4:4:43, 4 CP Mode 16 Video output 30-bit 4:4:43, 4 CP Mode 17 Video output 30-bit 4:4:43, 4 CP Mode 18 Video output 30-bit 4:4:43, 4 CP Mode 19 Video output 30-bit 4:2:23, 4
1 2
29
28
27
26
Output of Data Port Pins P[29:20] 25 24 23
22
21 -
20 -
CHB[7:0] (for example, R[7:0] or Cr[7:0])
CHA[7:0] (for example, G[7:0] or Y[7:0])
-
-
CHC[9:0] (for example, B[9:0] or Cb[9:0])
CHB[9:0] (for example, R[9:0] or Cr[9:0])
CHB[9:0] (for example, R[9:0] or Cr[9:0])
CHA[9:0] (for example, G[9:0] or Y[9:0])
CP processor uses digitizer or HDMI as input. Maximum pixel clock rate of 54 MHz. 3 Maximum pixel clock rate of 170 MHz for the analog digitizer. 4 Maximum pixel clock rate of 165 MHz for HDMI.
Rev. B | Page 20 of 28
AD9388A
REGISTER MAP ARCHITECTURE
The AD9388A registers are controlled via a 2-wire serial (I2C-compatible) interface. The AD9388A has eight maps, each with a unique I2C address. The state of the ALSB pin (Pin 13) sets Bit 2 of each register map address in Table 10. Table 10. AD9388A Map Addresses
Register Map User Map User Map 1 User Map 2 VDP Map Reserved Map HDMI Map Repeater/KSV Map EDID Map Address with ALSB = Low 0x40 0x44 0x60 0x48 0x4C 0x68 0x64 0x6C Address with ALSB = High 0x42 0x46 0x62 0x4A 0x4E 0x6A 0x66 0x6E Programmable Address Not programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Location at Which Address is Programmable N/A User Map 2, Register 0xEB User Map, Register 0x0E User Map 2, Register 0xEC User Map 2, Register 0xEA User Map 2, Register 0xEF User Map 2, Register 0xED User Map 2, Register 0xEE
USER MAP
USER MAP 1
USER MAP 2
VDP MAP
SA: 0x40
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SCL SDA
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SA: PROGRAMMABLE
SA: PROGRAMMABLE
HDMI MAP
EDID MAP
Figure 7. Register Map Access Through Main I2C Port
Rev. B | Page 21 of 28
06915-007
REPEATER/ KSV MAP
RESERVED MAP
AD9388A
TYPICAL CONNECTION DIAGRAM
Figure 8. Typical Connection Diagram
Rev. B | Page 22 of 28
06915-008
AD9388A
RECOMMENDED EXTERNAL LOOP FILTER COMPONENTS
Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 9 and Figure 10.
ELPF 70 1.69k 10nF
AUDIO_ELPF 102 1.5k 8nF
06915-009
82nF
PVDD = 1.8V
80nF
PVDD = 1.8V
Figure 9. ELPF Components
Figure 10. AUDIO_ELPF Components
Rev. B | Page 23 of 28
06915-010
AD9388A AD9388A/ADV7441A EVALUATION PLATFORM
Analog Devices has developed a new evaluation platform for the AD9388A/ADV7441A decoders. The evaluation platform consists of a motherboard and two daughterboards. The motherboard features a Xilinx FPGA for digital processing and muxing functions. The motherboard also features three AD9742s (12-bit DACs) from Analog Devices. This allows the user to drive a VGA monitor with just the motherboard and front-end board. The back end of the platform can be connected to a specially developed Analog Devices video output board. This modular board features an ADV7341 encoder and AD9889B HDMI transmitter. The front end of the platform consists of an EVALAD9388AFEZ_x or EVAL-ADV7441AFEZ_x board. This board feeds the digital outputs from the decoder to the FPGA on the motherboard. The EVAL-AD9388AFEZ_x or EVALADV7441AFEZ_x board comes with one of the pin-compatible decoders shown in Table 11.
Table 11. Front-End Modular Board Details
Front-End Modular Board Model
EVAL-ADV7441AFEZ_1 EVAL-ADV7441AFEZ_2 EVAL-AD9388AFEZ_1 EVAL-AD9388AFEZ_2 EVAL-AD9388AFEZ_3
On-Board Decoder ADV7441ABSTZ-170 ADV7441ABSTZ-5P AD9388ABSTZ-170 AD9388ABSTZ-5P AD9388ABSTZ-A5
HDCP License Required Yes No Yes No Yes
AUDIO 96-PIN CONNECTOR
ATV MOTHERBOARD VIDEO INPUT BOARD EVAL-AD9388AFEZ_x OR EVAL-ADV7441AFEZ_x
AVI 168-PIN CONNECTOR AD9388A/ADV7441A DECODER
Xilinx FPGA
VGA OUTPUT
ANALOG AND DIGITAL VIDEO INPUTS AVO 168-PIN CONNECTOR
VIDEO OUTPUT BOARD
CVBS
AD9889B
ADV7341
Y/C
HDMI
YPrPb
Figure 11. Functional Block Diagram of Evaluation Platform
Rev. B | Page 24 of 28
06915-101
AD9388A OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
144 1 PIN 1
22.20 22.00 SQ 21.80
109 108
TOP VIEW
(PINS DOWN)
20.20 20.00 SQ 19.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0
36 37 72
73
0.08 COPLANARITY
VIEW A
ROTATED 90 CCW
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
051706-A
COMPLIANT TO JEDEC STANDARDS MS-026-BFB
Figure 12. 144-Lead Low Profile Quad Flat Package [LQFP] (ST-144) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9388ABSTZ-170 1, 2 AD9388ABSTZ-1101, 2 AD9388ABSTZ- 5P1, 3, 4 AD9388ABSTZ-A51, 2, 5 EVAL-AD9388AFEZ_11, 2, 6 EVAL-AD9388AFEZ_21, 4, 7 EVAL-AD9388AFEZ_31, 2, 8
1 2
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] 144-Lead Low Profile Quad Flat Package [LQFP] Front End Evaluation Board Front End Evaluation Board Front End Evaluation Board
Package Option ST-144 ST-144 ST-144 ST-144
Z = RoHS Compliant Part. This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC for licensing requirements) to purchase any components with internal HDCP keys. 3 Speed Grade: 5 = 170 MHz, HDCP functionality: P = no HDCP functionality (pro version). 4 Professional version for nonHDCP encrypted applications. User is not required to be a HDCP adopter. 5 Speed Grade: 5 = 170 MHz, input configuration: A = 1 analog (AIN1, AIN2, AIN3, HS_IN/CS_IN, VS_IN, SOG, and SOY), 1 digital (1 HDMI port). 6 Front-end board for new evaluation platform; fitted with AD9388ABSTZ-170 decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on the evaluation platform. 7 Front-end board for new evaluation platform; fitted with AD9388ABSTZ-5P decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on the evaluation platform. 8 Front-end board for new evaluation platform; fitted with AD9388ABSTZ-A5 decoder. See the AD9388A/ADV7441A Evaluation Platform section for details on the evaluation platform.
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AD9388A NOTES
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AD9388A NOTES
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AD9388A NOTES
(c)2007-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06915-0-7/08(B)
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